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♦讀周期
Read cycle

電平高于VIH(min)且 電平低于VIL(max)時(shí)，操作定義為讀周期。讀操作訪問(wèn)時(shí)間定義為片選信號(hào)、輸出使能和地址中較晚有效信號(hào)到來(lái)的時(shí)間和輸出有效數(shù)據(jù)的時(shí)間之差。
When level is higher than VIH(min) and level is lower than VIL(max), the operation is defined as read cycle. Read operation access time is defined as difference between arrival time of valid chip select signal, output enable signal and address signal that arrives latest, and the time of valid data output.

讀操作方式1為地址變化讀取，如圖7-1所示，是在片選有效且 時(shí)由輸入地址的變化觸發(fā)的。當(dāng)滿足指定的時(shí)間條件tAVQV時(shí)，DQn(7:0)會(huì)輸出有效數(shù)據(jù)。整個(gè)周期內(nèi)輸出都保持有效狀態(tài)。只要片選信號(hào)和輸出信號(hào)都處于使能狀態(tài)，地址的輸入可以以最小讀周期tAVAV的頻率變化。
Read Operation Mode 1 is address change read, as shown in Fig. 7-1, which is triggered by address changes when chip select is valid and . When the specified time condition tAVQVis met, DQn(7:0) will output valid data. Output maintains valid throughout the whole cycle. As long as chip select signal and output signal are both enabled, the address inputs can vary with the frequency of the minimum read cycle tAVAV.

讀操作方式2為片選控制讀取，如圖7-2所示，是在 ，且地址在整個(gè)周期內(nèi)維持穩(wěn)定的情況下由 信號(hào)觸發(fā)。當(dāng)滿足指定的時(shí)間條件tETQV時(shí)，可訪問(wèn)到A(18:0)給出的地址并在DQn(7:0)上輸出有效數(shù)據(jù)。
Read Operation Mode 2 is chip select control read, as shown in Fig. 7-2, which is triggered by signal when and on condition that the address maintains stable throughout the whole cycle. When the specified time condition tETQVis met, the address given by A(18:0) can be accessed and valid data will be output on DQn(7:0).